1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to temperature management in three-dimensional die configurations.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are reduced with the introduction of every new circuit generation, thereby resulting in currently available integrated circuits formed by volume production techniques with critical dimensions of 50 nm or less and having an improved degree of performance in terms of speed and/or power consumption. Hence, the reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors, interconnect structures and the like, are typically formed in integrated circuits as required by the basic circuit layout. Due to the reduced dimensions of the active circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
Typically, as the number of circuit elements, such as transistors and the like, per unit area increases in the device level of a corresponding semiconductor device, the number of electrical connections associated with the circuit elements in the device level also increases, typically even in an over-proportional manner, thereby requiring complex interconnect structures which may be provided in the form of metallization systems including a plurality of stacked metallization layers. In these metallization layers, metal lines, providing the inner level electrical connection, and vias, providing intra level connections, may be formed on the basis of highly conductive metals, such as copper and the like, in combination with appropriate dielectric materials so as to reduce the parasitic RC (resistive capacitive) time constants, since, in sophisticated semiconductor devices, typically, signal propagation delay may be substantially restricted by the metallization system rather than the transistor elements in the device level. However, expanding the metallization system in the height dimension to provide the desired density of interconnect structures may be restricted by the parasitic RC time constants and the constraints imposed by the material characteristics of sophisticated low-k dielectrics. That is, typically, a reduced dielectric constant is associated with reduced mechanical stability of these dielectric materials, thereby also restricting the number of metallization layers that may be stacked on top of each other in view of yield losses during the various fabrication steps and the reduced reliability during operation of the semiconductor device. Thus, the complexity of semiconductor devices provided in a single semiconductor chip may be restricted by the capabilities of the corresponding metallization system, and in particular by the characteristics of sophisticated low-k dielectric materials, since the number of metallization layers may not be arbitrarily increased.
For this reason, it has also been proposed to further enhance the overall density of circuit elements for a given size or area of a respective chip package by stacking two or more individual semiconductor chips, which may be fabricated in an independent manner, however, with a correlated design so as to provide, in total, a complex system, while avoiding many of the problems encountered during the fabrication process for extremely complex semiconductor devices on a single chip. For example, appropriately selected functional units, such as memory areas and the like, may be formed on a single chip in accordance with well-established manufacturing techniques, including the fabrication of a corresponding metallization system, while other functional units, such as a fast and powerful logic circuitry, such as a central processing unit (CPU), may be formed independently as a separate chip, wherein, however, respective interconnect systems may enable a subsequent stacking and attaching of the individual chips so as to form an overall functional circuit, which may then be packaged as a single unit. In other cases, power circuitry operated at moderately high voltages and having a high power consumption may be combined with sensitive control circuits, wherein both functional units may be provided in separate chips. Thus, a corresponding three-dimensional configuration may provide increased volume density of circuit elements and metallization features with respect to a given area of a package, since a significantly larger amount of the available volume in a package may be used by stacking individual semiconductor chips. Although this technique represents a promising approach for enhancing the volume packing density and functionality for a given package size for a given technology standard, while avoiding extremely critical manufacturing techniques, for instance in view of stacking a large number of highly critical metallization layers, the heat management of these three-dimensional chip arrangements may be difficult, in particular when high power consuming chips are included.
For example, in sophisticated CPU devices, the static and dynamic power consumption may result in significant waste heat that has to be dissipated from the device, which is typically accomplished by providing an efficient heat dissipation path from the semiconducting material to a periphery via a package substrate, which in turn may be contacted with an appropriate heat sink, such as a cooler fan and the like. In this case, the rear side of the semiconductor substrate may be efficiently cooled on the basis of the external heat sink via the substrate material and the package substrate. In a stacked device configuration, in which, for instance, a sophisticated memory device, such as a dynamic RAM device, may be incorporated, the efficient thermal coupling of the rear side of the CPU with the external efficient heat sink may no longer be available, since the substrate of the memory circuit may be attached to the high power semiconductor device, thereby significantly reducing the overall heat dissipation capability. In this case, the stacked device configuration may provide superior overall volume packing density, while, however, actual performance may be reduced, at least in an operating phase, in which significant power consumption is required in the CPU. Consequently, in some conventional approaches, dedicated material or material systems are implemented into the stacked device configuration, for instance between the rear sides of the semiconductor substrates, in order to efficiently enhance heat dissipation from the high power device, for instance the CPU, into the device having a significantly reduced power consumption in order to finally connect to an external heat sink. In other cases, additional measures may be taken to enhance the heat dissipation capability via a metallization system of the high power device, wherein, in particular in sophisticated applications, corresponding low-k dielectric materials provided in complex metallization systems may significantly reduce the overall power dissipation capabilities, thereby rendering this approach a less attractive option for stacked device configurations, in which sophisticated high power devices, such as complex CPUs, are to be used.
Generally, the concept of transferring an increased amount of heat from the high power device into the low power device may allow a certain reduction of the overall temperature gradient in the stacked device configuration, wherein, however, the limited heat dissipation capabilities of corresponding material systems provided between the substrates of the high power device and low power device, in combination with the restricted heat dissipation capability of the metallization system of the low power device, may result in a limited overall heat dissipation capability, thereby also restricting performance of the stacked device configuration.
The present disclosure is directed to various devices and methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.